1. Field of the Invention
This invention relates to a manufacturing method of leadframes and semiconductor devices.
a leadframe in which.
2. Related Art
There is known a conventional semiconductor device having a plurality of terminals with an area array shape that is formed by conducting etching process on a leadframe material 50 made of cupper or cupper alloy. As a manufacturing method of such semiconductor device, for example, the manufacturing method disclosed in JP 2001-24135A is known.
This manufacturing method is, as shown in FIGS. 7A to 7G, constituted by a plating layer formation step of forming plating layers on upper side terminal portions 60 (wire bonding portions 59) and an outer frame 53 surrounding the upper side terminal portions 60 on a front side of the leadframe material 50 as well as forming plating layers on lower side terminal portions 67 formed on a rear side of the leadframe material 50 corresponding to the upper side terminal portions 60 (external correction terminal portions); a first etching step of performing etching process onto the front side of the leadframe material 50 with a plating layer 57 as resist mask up to a predetermined depth so that a leadframe 70 is formed so as to protrude the outer frame 53 and the wire bonding portions 59; an assembling step of mounting a semiconductor element 64 on the leadframe 70 and connecting the semiconductor element 64 and the wire bonding portions 59 with bonding wires 65; a resin encapsulating step of encapsulating the front side of the leadframe 70 including the semiconductor element 64, bonding wire 65 and the protruded outer frame 53 with resin 66; a second etching step of performing etching process onto the rear side of the leadframe 70 with a plating layer 58 as resist mask formed thereon to separate the lower side terminal portions 67. First and second circuit patterns 55, 56 and an element mounting portion 61 are formed on the leadframe material 50.
However, in this manufacturing method, there is a problem that plating burrs 62,63 are generated due to erosion by etching solution at edges of the upper terminal portions 60 and the outer frame 53 that are protruded in the first etching step.
These plating burrs 62,63 could cause peeling of plating in later steps of manufacturing. Further, they could affect etching accuracy in later stages, resulting in a problem of decrease in reliability of the semiconductor devices such as causing a short circuit.
In JP 2007-48981A, water jet and ultrasonic wave are suggested as means for removing plating burrs generated in the above manufacturing method. When the water jet is used, the plating burrs in a half-etching area A in which terminals are formed in FIG. 8 are hit by the water jet with water pressure applied from the upper side as well as with the reflection of water pressure at side faces of the terminals, so that the plating burrs are removed. However, on the outer frame area B including the outer frame 53 and pilot holes 54, the reflection of the water jet applied from the upper side is hardly received, as a result, the plating burrs generated in the outer frame 53 and the pilot holes 54 to which the water pressure of the water jet is subjected cannot be removed sufficiently. Further, when the ultrasonic wave is used instead of the water jet, another problem could be caused that the leadframe is deformed because the strength is low in the half-etching area which is formed by reducing the thickness of the leadframe material by the etching conducted in the first etching step. Thus, any of these means for removing the plating burrs are not sufficient to remove the plating burrs reliably over the entire surface of the leadframe.